A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit can be stored using a first charge storing region on a first “side” of the memory device (or normal bit) and a second bit can be stored using a second charge storing region on a second “side” of the memory device (or complimentary bit).
In a conventional charge trapping dielectric flash memory device, the charge storing regions are part of a non-conductive charge trapping layer that is disposed between a bottom (or tunnel) dielectric layer and a top dielectric layer. This dielectric stack can be formed over a P type silicon substrate having a first and a second bit line disposed therein. A conductive word line made from N type or N+ type polycrystalline silicon (also referred to as poly-silicon or poly-Si) is formed over the dielectric stack and serves as a gate electrode. The bit lines can be formed from N+ conductivity type material and, upon application of appropriate voltages to the word line and/or the bit lines, the bit lines can respectively function as a source and a drain with an active channel region defined therebetween.
By the appropriate application of voltage potentials to the gate electrode, the source and/or the drain, each charge storing region can be programmed to store an amount of charge corresponding to a programmed, or charged, data state (as opposed to an unprogrammed, or blank, data state). Programming of the charge storage regions involves channel hot electron (CHE) injection where electrons traveling within the channel and that have a sufficient amount of energy to overcome the barrier height of the tunnel dielectric layer, can become injected into the charge trapping layer where they become trapped.
A conventional charge trapping dielectric memory device, (e.g., having an N+ polysilicon gate electrode) can only be erased using the conventional technique of “hot hole injection” (sometimes referred to as band-to-band (BTB) hot hole injection). In hot hole injection, a gate voltage of approximately −4 to −8 volts is applied along with a drain voltage on the order of 4.5 to 6.0 volts, while the source is floated or grounded to erase one of the memory cells (typically the normal bit). Conversely, the complementary bit cell is erased by floating the drain and applying the appropriate voltages to the source and the gate.
With such erase conditions, a BTB tunnel current is created under the gate. Holes are generated under these conditions and accelerate from the N-type drain region into the P-type body. The generated holes are accelerated in the electrical field created near the P-N drain/body junction. Some of the accelerated holes surmount the oxide to silicon interface between the substrate and the bottom oxide and are injected into the nitride charge storing layer to displace electrons (e.g., by recombination) and erase the cell.
However, as the hot holes bombard the interface between the substrate and the bottom tunnel oxide, the interface and the bottom tunnel oxide can become damaged. This damage leads to data retention problems. For instance, degraded data retention reliability over program/erase cycling can occur due to stored charge leakage through the damaged tunnel oxide. As a result, a charge amount that has been “programmed” into one or both of the charge trapping regions can be reduced over time. In certain circumstances, enough charge can be lost that the data retention capability of the memory device is compromised.
Another erase mechanism used in floating gate devices (e.g., charge is stored in a conductive polysilicon layer rather than a dielectric layer), is channel erase (also commonly referred to as a Fowler-Nordheim (FN) erase). However, FN erase is problematic for conventional charge trapping dielectric memory devices. More specifically, the vertical electric fields present during the erase not only cause electrons to be pushed out from the charge storing layer to the substrate, but also cause electrons to flow from the N+ gate through the top oxide and into the charge storing layer at approximately the same tunneling rate. Therefore, while there is a net current from the gate electrode to the substrate, charge is not erased effectively from the charge storing layer.
In view of the foregoing, there is a need in the art for improved dielectric charge trapping memory devices that can retain trapped charge amounts over a longer period of time.